| - MS, or PhD in Electrical or Computer Engineering or Computer Science
- 6+ years of ASIC design and verification and software programming experience - 2+ years experience in advanced verification methodology, such as VMM or AVM; have developed coverage driven constrained random verification environment(s) and test cases. - Experience in using reference models to verify hardware - Extensive RTL development experience (Verilog or VHDL) is a plus - familiarity with MIPS or ARM architecture, C level and ASM level debugging, scripting language is a plus - Ability to lead and take ownership of process/methodology development and execution - Well organized, methodical, and detail oriented - Team player, and easy to work with - Fluent in English |
